1. Field of the Invention
The present invention relates to apparatus and processes for packaging microelectronic dice. In particular, the present invention relates to a packaging technology that encapsulates a microelectronic die within a microelectronic package core.
2. State of the Art
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As these goals are achieved, microelectronic dice become smaller. Of course, the goal of greater packaging density requires that the entire microelectronic die package be equal to or only slightly larger (about 10% to 30%) than the size of the microelectronic die itself. Such microelectronic die packaging is called a xe2x80x9cchip scale packagingxe2x80x9d or xe2x80x9cCSPxe2x80x9d.
As shown in FIG. 20, true CSP involves fabricating build-up layers directly on an active surface 204 of a microelectronic die 202. The build-up layers may include a dielectric layer 206 disposed on the active surface 204. Conductive traces 208 may be formed on the dielectric layer 206, wherein a portion of each conductive trace 208 contacts at least one contact 212 on the active surface 204. External contacts, such as solder balls or conductive pins for contact with an external component (not shown), may be fabricated to electrically contact at least one conductive trace 208. FIG. 20 illustrates the external contacts as solder balls 214 which are surrounded by a solder mask material 216 on the dielectric layer 206. However in such true CSP, the surface area provided by the microelectronic die active surface 204 generally does not provide enough surface for all of the external contacts needed to contact the external component (not shown) for certain types of microelectronic dice (e.g., logic).
Additional surface area can be provided with the use of an interposer, such as a substrate (substantially rigid material) or a flex component (substantially flexible material). FIG. 21 illustrates a substrate interposer 222 having a microelectronic die 224 attached to and in electrical contact with a first surface 226 of the substrate interposer 222 through small solder balls 228. The small solder balls 228 extend between contacts 232 on the microelectronic die 224 and conductive traces 234 on the substrate interposer first surface 226. The conductive traces 234 are in discrete electrical contact with bond pads 236 on a second surface 238 of the substrate interposer 222 through vias 242 that extend through the substrate interposer 222. External contacts 244 are formed on the bond pads 236 (shown as solder balls). The external contacts 244 are utilized to achieve electrical communication between the microelectronic die 224 and an external electrical system (not shown).
The use of the substrate interposer 222 requires number of processing steps, which increases the cost of the package. Additionally, the use of the small solder balls 228 presents crowding problems which can result in shorting between the small solder balls 228 and can present difficulties in inserting underfill material between the microelectronic die 224 and the substrate interposer 222 to prevent contamination and to increase mechanical reliability. Furthermore, necessity of having two sets of solder balls (i.e., small solder balls 228 and external contacts 244) to achieve connection between the microelectronic die 224 and the external electrical system decreases the overall performance of the microelectronic die package.
Therefore, it would be advantageous to develop new apparatus and techniques to provide additional surface area to form traces for use in CSP applications and eliminate the necessity of the substrate interposer.